Automating microfluidic chip design: Hybrid approach combines machine learning with fluid mechanics

Researchers led by Assoc. Prof. Dr. Savaş Taşoğlu from the Department of Mechanical Engineering at Koç University have ...
Nanowerk

Thermonat makes nanoscale thermal prediction practical for real-world chip design

Heat limits sub-10 nm chips, but current tools miss nanoscale effects or run too slowly. New modeling bridges atom-level ...
Electronic Design

Designing a Chip with Open-Source Tools: The Development of Silicluster

Open-source tools and multi-project wafer (MPW) shuttles democratize chip design for low cost. Small circuits, both analog and digital, are accommodated by embedding them as “tiles” or “clusters” into ...
Electronic Design

How AI is Supercharging Chip Design Workflows

For decades, the design of leading-edge chips has been a high-wire act—balancing tight deadlines, sophisticated workflows, and the relentless need to consult scattered, often outdated, sources of ...
Business Wire

Cadence Partners with TSMC to Power Next-Generation Innovations Using AI Flows and IP for TSMC Advanced Nodes and 3DFabric

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced major advancements in chip design automation and IP, driven by its long-standing relationship with TSMC to develop advanced ...
Semiconductor Engineering

Integrating Data From Design, Manufacturing, And The Field

Chip design is starting to include more options to ensure chips behave reliably in the field, boosting the ability to tweak both hardware and software as chips age. The basic problem is that as ...
Semiconductor Engineering

How 3D-IC Will Change Chip Design

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product ...