An efficient method of Packaging Silicon IP and then testing /synthesizing it for multiple configurations has been described. It has been shown how with the help of a packaging/regression environment ...
We’ll let you decide: “Is it an IP test evolution or revolution?” Whatever the outcome, change is afoot on the way to develop test, supply test to others, reuse test, integrate test features, validate ...
Today’s PCIe verification engineers have to trade-off between verification completeness and demanding time to market, and the new Gen4 specification makes it more challenging. This video highlights ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results